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AMD Slides Detail Bulldozer (Zambezi-FX) and AM3+ Platform Architecture
AMD Slides Detail Bulldozer (Zambezi-FX) and AM3+ Platform Architecture-August 2024
Aug 11, 2025 3:43 AM

AMD has detailed its Upcoming AM3+ and Bulldozer CPU Platform at this Years Hot Chips event inCalifornia. The company showed tons of new slides which provides information on the Bulldozer Core Die, Power Saving and Turbo Core 2.0 features.

The Zambezi-FX Processors detailed by AMD in the slides was a FX-8150 CPU which consists of Four BulldozerModules each consisting of two integer cores plus floating point core. The floating point core works at 256 bit or two 128 bit units which shows Bulldozer would support new AVX instructions, Each Module is connected with 2MB L2 Cache (8MB L2 Total) and 32KB L1 Cache (128 KB total) while the CPU features a total of 8MB L3 Cache and two 72 bit channels are connected to the memory featuring64-bit data lines and 8-bit error correction.

While the two integer cores share all functions howeverL1 data cache and theinteger pipeline would not beavailablefor each individual core butcomplete floating point units and the L2 cache areavailablefor theseparatecores. The 8MB L3 Cache and the two 72-bit wide memory channels are controlled by the integrated Northbridge. The Following Slides Details the AMD CPU Die:

Next on is the AM3+ Platform, The AM3+ Socket allows support for Low Voltage DRAM,Hyper transportlink with Higher Frequency due to increased ILDT current (2.0A Per Gen3 Interface link) and also increase IDDR current upto 4.0A. The new socket allows compatibility for older gen AM3 Phenom based processors and provides 2 Memory Channels (Unbuffered DIMMS) with Max Frequency support of 1866+ Mhz. The HyperTransport link wit increased ILDT currents provides a maximum of 5.2GT/s.The Socket would be made compatible with the following AMD's 9 Series Chipset:

AMD 990FXAMD 990XAMD 970AMD SB950

AMD would alsoimplementTurbo Core 2.0 in its Next Gen Bulldozer Cores which allow for max level of performance to be utilized out of the Processors. When TDP Headroom isavailable in a certain workload, All of the Cores would Automatically increase their clock speeds. Similarly when C6 Power Saving feature puts Half Bulldozer Cores in Sleep mode during a lightthreadedworkload, The Active Bulldozer Cores can increase their clocks twice as much beyond the normal Turbo Core limit. We already detailed AMD's Bulldozer to feature Turbo Core upto 1Ghz here.

Also SemiAccurate also leaked the Die Size of a Bulldozer Processor which you can see below:

You can check out more details in the slides below:

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