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AMD Zen 5 & Zen 5C EPYC CPU Rumors: Turin With 16 CCDs 128 Cores, Turin-Dense With 12 CCDs 192 Cores, Turin-X With 1.5 GB L3 Cache
AMD Zen 5 & Zen 5C EPYC CPU Rumors: Turin With 16 CCDs 128 Cores, Turin-Dense With 12 CCDs 192 Cores, Turin-X With 1.5 GB L3 Cache-April 2024
Apr 1, 2026 2:34 PM

New rumors of AMD's Zen 5 & Zen 5C EPYC CPU family, codenamed Turin, have leaked out which point out up to 16 CCDs & 192 cores.

AMD To Offer Up To 192 Cores With Next-Gen EPYC CPUs: Turin With 16 Zen 5 CCDs, Turin-Dense With 12 Zen 5C CCDs & Turin-X With 1.5 GB L3 Cache

The latest rumors come from Weibo leaker, 剧毒术士马文, who seems to have acquired an internal AMD roadmap that reveals several next-generation Turin designs based on the Zen 5 and Zen 5C core architecture. Most of this information had already been talked about by Moore's Law is Dead but we get to learn a few more details such as the max cache counts and the CCD configurations.

AMD EPYC Turin & Turn-X With Zen 5: Up To 128 Cores, 4nm Process

Starting with the first family, we have the AMD EPYC Turin (Classic) which will stick with the chiplet design and house up to 128 cores, 256 threads, and TDPs of up to 500W which can be configurable on certain SKUs up to 600W (as revealed in today's Gigabyte leak). In a previous leak, it was shown that the EPYC Turin chips would feature the same L2 and L3 cache as Zen 4 with a small upgrade to the L1 cache.

Since these chips are packaged on a 4nm process node, that will lead to a smaller die area per core, allowing AMD to cram up to 16 CCDs within the same package that retains its socket compatibility with SP5 platforms.

AMD To Offer Up To 192 Cores With Next-Gen EPYC CPUs: Turin With 16 Zen 5 CCDs, Turin-Dense With 12 Zen 5C CCDs & Turin-X With 1.5 GB L3 Cache 2

Moving on, we have the AMD EPYC Turin-X chips which will be outfitted with a 3D V-Cache. These chips will retain the 64MB of 3D V-Cache per CCD which totals 1024 MB across the 16 CCDs & 512 MB of standard L3 cache. Totaling up to 1536 MB or 1.5 GB of L3 cache. If we combine the L2 cache which is 1 MB per core or 128 MB in total, that increases to 1664 MB of total cache which is still not including the L1 cache. That's a 33% higher cache compared to the upcoming Genoa-X CPU family.

AMD EPYC Turin Dense & Turin AI With Zen 5C: Up To 192 Cores, 3nm Process

Moving over to the Zen 5C side of things, we first have the AMD EPYC Turin Dense chips which will be succeeding Bergamo. Turin Dense isn't an official name for now but it is expected to utilize the 3nm Zen 5C cores in up to 192 core SKUs. These chips will feature up to 500W TDPs but the most interesting thing is that they are expected to hit production before the standard Turin chips. MLID states that this is due to AMD speeding things to compete directly against Intel's Sierra Forest 144 core chips which are also expected around the same time in the first half of 2024.

The overall configurations look like the following:

AMD EPYC Turin-Classic - 16 Zen 5 CCDs / 128 Cores / 256 Threads / 512 MB L3 CacheAMD EPYC Turin-Dense - 12 Zen 5C CCDs / 192 Cores / 384 Threads / 384 MB L3 CacheAMD EPYC Turin-X 3D - 16 Zen 5 CCDs / 128 Cores / 256 Threads / 1536 MB L3 Cache

AMD's first Zen 5 CPUs are expected for next year with the company already revealed Ryzen 8000 consumer processors for a 2024 launch. The first EPYC Turin CPUs should also appear next year & we can see Dense & "X" variants in the following year.

AMD EPYC CPU Families:

Family NameAMD EPYC VeniceAMD EPYC Turin-DenseAMD EPYC Turin-XAMD EPYC TurinAMD EPYC SienaAMD EPYC BergamoAMD EPYC Genoa-XAMD EPYC GenoaAMD EPYC Milan-XAMD EPYC MilanAMD EPYC RomeAMD EPYC Naples
Family BrandingEPYC 11K?EPYC 10K?EPYC 10K?EPYC 10K?EPYC 8004EPYC 9004EPYC 9004EPYC 9004EPYC 7004EPYC 7003EPYC 7002EPYC 7001
Family Launch2025+2025?2025?202420232023202320222022202120192017
CPU ArchitectureZen 6?Zen 5CZen 5Zen 5Zen 4Zen 4CZen 4 V-CacheZen 4Zen 3Zen 3Zen 2Zen 1
Process NodeTBD3nm TSMC?4nm TSMC4nm TSMC5nm TSMC4nm TSMC5nm TSMC5nm TSMC7nm TSMC7nm TSMC7nm TSMC14nm GloFo
Platform NameTBDSP5SP5SP5SP6SP5SP5SP5SP3SP3SP3SP3
SocketTBDLGA 6096 (SP5)LGA 6096 (SP5)LGA 6096LGA 4844LGA 6096LGA 6096LGA 6096LGA 4094LGA 4094LGA 4094LGA 4094
Max Core Count384?19212812864128969664646432
Max Thread Count768?38425625612825619219212812812864
Max L3 CacheTBD384 MB1536 MB384 MB256 MB256 MB1152 MB384 MB768 MB256 MB256 MB64 MB
Chiplet DesignTBD12 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD8 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (2 CCX's per CCD) + 1 IOD4 CCD's (2 CCX's per CCD)
Memory SupportTBDDDR5-6000?DDR5-6000?DDR5-6000?DDR5-5200DDR5-5600DDR5-4800DDR5-4800DDR4-3200DDR4-3200DDR4-3200DDR4-2666
Memory ChannelsTBD12 Channel (SP5)12 Channel (SP5)12 Channel6-Channel12 Channel12 Channel12 Channel8 Channel8 Channel8 Channel8 Channel
PCIe Gen SupportTBDTBDTBDTBD96 Gen 5128 Gen 5128 Gen 5128 Gen 5128 Gen 4128 Gen 4128 Gen 464 Gen 3
TDP (Max)TBD480W (cTDP 600W)480W (cTDP 600W)480W (cTDP 600W)70-225W320W (cTDP 400W)400W400W280W280W280W200W

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