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AMD Zen 6 Architecture Rumored To Power EPYC Venice Server CPUs: Over 200 Cores, Completely Redesigned L2/L3 Cache & HBM SKUs
AMD Zen 6 Architecture Rumored To Power EPYC Venice Server CPUs: Over 200 Cores, Completely Redesigned L2/L3 Cache & HBM SKUs-February 2024
Feb 13, 2026 4:25 AM

The successor to AMD's EPYC Turin CPUs which will feature Zen 5 cores is rumored to be called EPYC Venice and will feature Zen 6 architecture, reports Moore's Law is Dead.

AMD EPYC Venice Server CPUs Rumored To Feature Over 200 Zen 6 Cores With Redesigned L2/L3 Cache & HBM SKUs

While the details are quite vague at the moment considering this product isn't expected to launch till 2025+, it looks like MLID got his hands on very early details regarding the codename and AMD's marketing has come up with 'Venice' for its next-generation EPYC lineup. Named after the capital of the Veneto region in northeastern Italy, the EPYC Venice lineup is expected to be a huge update for servers.

Some details that are shared include references to the AMD Zen 6 cores though it is not known if the red team will continue with its Zen naming scheme beyond 2025 or move to something else. The server segment will continue with the EPYC naming convention. It is said that Zen 6 or the x86 architecture after Zen 5 will make use of a very hybrid core design approach and can offer over 200 cores (a conservative estimate) with rumors of up to 384 cores per socket. There's no mention if the CPU will be compatible with the SP5 platform but it looks like Turin and its follow-up on Zen 5C might be the last EPYC chips for the upcoming platform. The SP5 socket will last till 2025 which is a good timeframe to provide an update.

AMD EPYC Milan-X processor upgrade for cloud workloads gain significant improvements in Microsoft Azure HBv3

As for the upgrades in the architecture itself, the leaker also stated that the AMD is expected to completely redesign the L2 and L3 cache system. The Infinity Cache architecture will also see a major change. Also, HBM will become the standard across most of the lineup and the memory standard will play a huge role in next-generation EPYC CPUs. The on-board HBM hybrid design integrated within EPYC can be used to scale IPC within the same core count. One interesting and key detail is that Tom also expects Zen 5-based EPYC offerings to be amongst the first AMD EPYC server products to feature HBM designs while EPYC Venice will standardize it across multiple SKUs.

In the end, while all of this sounds great, one should remember we are talking about products that launch 3-4 years from now and a lot can change in the meantime. But it looks like EPYC Venice from AMD might indeed be a thing and we can't wait to see it in action a few years from now!

AMD EPYC CPU Families:

Family NameAMD EPYC VeniceAMD EPYC Turin-DenseAMD EPYC Turin-XAMD EPYC TurinAMD EPYC SienaAMD EPYC BergamoAMD EPYC Genoa-XAMD EPYC GenoaAMD EPYC Milan-XAMD EPYC MilanAMD EPYC RomeAMD EPYC Naples
Family BrandingEPYC 11K?EPYC 10K?EPYC 10K?EPYC 10K?EPYC 8004EPYC 9004EPYC 9004EPYC 9004EPYC 7004EPYC 7003EPYC 7002EPYC 7001
Family Launch2025+2025?2025?202420232023202320222022202120192017
CPU ArchitectureZen 6?Zen 5CZen 5Zen 5Zen 4Zen 4CZen 4 V-CacheZen 4Zen 3Zen 3Zen 2Zen 1
Process NodeTBD3nm TSMC?4nm TSMC4nm TSMC5nm TSMC4nm TSMC5nm TSMC5nm TSMC7nm TSMC7nm TSMC7nm TSMC14nm GloFo
Platform NameTBDSP5SP5SP5SP6SP5SP5SP5SP3SP3SP3SP3
SocketTBDLGA 6096 (SP5)LGA 6096 (SP5)LGA 6096LGA 4844LGA 6096LGA 6096LGA 6096LGA 4094LGA 4094LGA 4094LGA 4094
Max Core Count384?19212812864128969664646432
Max Thread Count768?38425625612825619219212812812864
Max L3 CacheTBD384 MB1536 MB384 MB256 MB256 MB1152 MB384 MB768 MB256 MB256 MB64 MB
Chiplet DesignTBD12 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD8 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (2 CCX's per CCD) + 1 IOD4 CCD's (2 CCX's per CCD)
Memory SupportTBDDDR5-6000?DDR5-6000?DDR5-6000?DDR5-5200DDR5-5600DDR5-4800DDR5-4800DDR4-3200DDR4-3200DDR4-3200DDR4-2666
Memory ChannelsTBD12 Channel (SP5)12 Channel (SP5)12 Channel6-Channel12 Channel12 Channel12 Channel8 Channel8 Channel8 Channel8 Channel
PCIe Gen SupportTBDTBDTBDTBD96 Gen 5128 Gen 5128 Gen 5128 Gen 5128 Gen 4128 Gen 4128 Gen 464 Gen 3
TDP (Max)TBD480W (cTDP 600W)480W (cTDP 600W)480W (cTDP 600W)70-225W320W (cTDP 400W)400W400W280W280W280W200W

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