Intel unveiled the details of its next-generation Sunny Cove architecture to press yesterday at the Intel Architecture Event along with the updated Core roadmap for 2019-2021. Intel has divided its approach to improving its Core product lineup into two branches: general purpose and special purpose. Sunny Cove is something that is the culmination of both these requirements and represents a leap up from Skylake.

Intel's Sunny Cove next-generation processors will succeed Skylake in 2019, Roadmap for 2020 and 2021 updated

Intel has tried to shift the conversation away from process nodes, unsuccessfully in the past (primarily because they helped cultivate that narrative, to begin with) and its refreshing to see an update that actually succeeds in doing so. Sunny Cove is a significant improvement over Skylake processors and all of it has to do with design innovation. The Sunny Cove next-generation processors will be deeper, wider and smarter – as per the details revealed during the event.

Before we go any further, here's the official blurb:

Intel introduced Sunny Cove, Intel’s next-generation CPU microarchitecture designed to increase performance per clock and power efficiency for general purpose computing tasks, and includes new features to accelerate special purpose computing tasks like AI and cryptography. Sunny Cove will be the basis for Intel’s next-generation server (Intel® Xeon®) and client (Intel® Core™) processors later next year. Sunny Cove features include:

Enhanced microarchitecture to execute more operations in parallel.New algorithms to reduce latency.Increased size of key buffers and caches to optimize data-centric workloads.Architectural extensions for specific use cases and algorithms. For example, new performance-boosting instructions for cryptography, such as vector AES and SHA-NI, and other critical use cases like compression and decompression.

Sunny Cove enables reduced latency and high throughput, as well as offers much greater parallelism that is expected to improve experiences from gaming to media to data-centric applications.

Sunny Cove processors have received a 50% increase in the size of the L1 data cache as well as a larger L2 cache. They also feature larger operations cache and a larger 2nd level translation lookaside buffer. The result is a processor that has received a significant increase in key structures can execute code with much more depth than Skylake.

Sunny Cove processors are also wider than Skylake. They have 5-wide allocations instead of 4 and 10 execution ports instead of 8. They have also received two times the L1 store bandwidth thanks to 4 AGU instead of 3 and 2 data stores. Not only that, but greater execution capability is now part of the architecture. SIMD, Shuffle and LEA units have been added to the Vector and Integer blocks.

New algorithms that can handle scale better and increase branch prediction accuracy (this reminds me, hardware mitigations for Spectre v1 are already shipping and Sunny Cove will include hardware mitigations for Spectre v2). The effective load latency has also been reduced.

The brand new architecture also has specialized improvements in areas such as cryptography, AI/machine learning compression, and decompression and vector processing. Memory capacity now supports 5-level paging and linear address space has been increased to 57 bits. Multi-Key Total Memory Encryption is also now available along with User Mode Instruction Prevention so that customers of cloud platforms feel more secure about someone just reading off the memory directly.

The new roadmap is as follows:

Sunny Cove will debut in 2019, featuring improved single threaded performance, scalability improvements, and a new instruction set. Willow cove will succeed it sometime in 2020 with a cache redesign, transistor optimizations, and more security features. Finally, Golden Cove will debut in 2021. On the Atom side, Tremont will debut in 2019 with improved single threaded performance, network server performance increase and battery life improvements. Gracemont will improve on single threaded performance and frequency as well as vector performance.

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