As a part of its Pre-HC34 (Hot Chips 34) presentation, Intel gave us a detailed explanation of it's next-generation CPUs, Meteor Lake, Arrow Lake, & Lunar Lake, which will be making use of the Foveros 3D packaging technology. The company also cleared away some confusion surrounding recent rumors regarding the process nodes that it plans to leverage for its multi-chiplet & multi-IP designs.
Intel Meteor Lake, Arrow Lake, Lunar Lake CPUs With 3D Foveros MCM Packaging Detailed: TSMC 5nm tGPU For 14th Gen & 3nm tGPU For 15th Gen
Beyond Alder Lake and Raptor Lake CPUs which are the first designs to feature a hybrid core layout, Intel is planning to utilize its 3D Foveros packaging to usher in its own multi-chiplet era. Chipzilla has planned on releasing three products that will leverage this technology. The next-generation processors include the 14th Gen Meteor Lake, 15th Gen Arrow Lake, and 16th Gen Lunar Lake families. Some of the main highlights of these CPUs would be:
Intel Next Generation 3D Client PlatformDisaggregated 3D Client architecture with CPU, GPU, SOC, and IO TilesBase tiles for Meteor Lake and Arrow Lake to interconnect tiles with FoverosOpen "Chiplet" ecosystem through universal chiplet interconnect express (UCIe)
Starting first with Intel Meteor Lake, the company showed off a brand new chip layout which gives us a better look at the various tiles or chiplets (as you like to refer to them) with various IPs. The quad-tile layout includes the CPU Tile, Graphics Tile, SOC Tile, and IOE Tile. Intel did disclose the specific nodes these tiles would be based upon. The main CPU tile will be using the "Intel 4" or 7nm EUV process node while the SOC Tile and IOE Tiles will be fabricated on TSMC's 6nm process node (N6). Intel calls Meteor Lake the first step into the chiplet ecosystem in the client segment.
The most speculative tile that has been so far had been the GPU tile that is otherwise known as tGPU. There have been rumors that Intel originally planned to use TSMC's 3nm process node but due to some issues, they changed the plans midway and tapped into TSMC's 5nm node instead. According to industry sources, this isn't the case and the tGPU for the Meteor Lake CPUs has always been a TSMC 5nm (N5) design.
Another aspect that was touched upon by Intel is pricing. With costs of next-gen wafer prices going up with every new node, the cost of developing a monolithic die is also going to go up. According to Intel itself:
If you were to take Meteor Lake as it is and design it monolithically on a leading process node, I would say it actually is extremely competitive with that if not actually cheaper.

The configuration shown here is also a mobile-specific chip with a 6+4 (6 P-Cores + 4 E-Cores) layout. You can also note that there are two D2D (Die-To-Die) links between the CPU/IOE Tile and the Graphics Tile leading into the SOC Tile. This is part of the Foveros 3D Packaging and the blue team states that there's a passive interposer on top of the main chiplets which is based on a 22nm (FFL) process from Intel itself. This interposer currently serves no purpose but the company plans to use active chiplets within it in the future with more advanced packaging technologies. The Intel Meteor Lake CPUs don't utilize EMIB technology.
Furthermore, Intel clarified that 14th Gen Meteor Lake & 15th Gen Arrow Lake CPUs are indeed heading to both Desktop and Mobile platforms. The Intel Meteor Lake CPUs are aiming for the 2023 release window while Arrow Lake will start shipping in 2024 as originally planned. Details on the next-generation LGA 1851 socketed platform for Meteor Lake & Arrow Lake CPUs can be found here.
Intel Meteor Lake-P (6+8) CPU Chip Layout:

As far as 16th Gen Lunar Lake CPUs are concerned, the family is said to be originally aimed at the 15W low-power mobile CPU segment however those original plans can always change since the product is still a few years away from launch. Furthermore, it won't be the first time Intel sticks with a mobile-only or partial-desktop release for a CPU family. We have already seen them do this with Broadwell and more recently with the Ice Lake and Tiger Lake CPU families.
Intel Mobility CPU Lineup:
| CPU Family | Lunar Lake | Arrow Lake | Meteor Lake | Raptor Lake | Alder Lake |
|---|---|---|---|---|---|
| Process Node (CPU Tile) | Intel 20A? | Intel 20A '5nm EUV" | Intel 4 '7nm EUV' | Intel 7 '10nm ESF' | Intel 7 '10nm ESF' |
| Process Node (GPU Tile) | TSMC 3nm? | TSMC 3nm | TSMC 5nm | Intel 7 '10nm ESF' | Intel 7 '10nm ESF' |
| CPU Architecture | Hybrid | Hybrid (Four-Core) | Hybrid (Triple-Core) | Hybrid (Dual-Core) | Hybrid (Dual-Core) |
| P-Core Architecture | Lion Cove? | Lion Cove | Redwood Cove | Raptor Cove | Golden Cove |
| E-Core Architecture | Skymont? | Skymont | Crestmont | Gracemont | Gracemont |
| LP E-Core Architecture (SOC) | Skymont? | Crestmont? | Crestmont? | N/A | N/A |
| Top Configuration | TBD | TBD | 6+8 (H-Series) | 6+8 (H-Series) 8+16 (HX-Series) | 6+8 (H-Series) 8+8 (HX-Series) |
| Max Cores / Threads | TBD | TBD | 14/20 | 14/20 | 14/20 |
| Planned Lineup | U Series? | H/P/U Series | H/P/U Series | H/P/U Series | H/P/U Series |
| GPU Architecture | Xe2-LPG (Battlemage) | Xe-LPG (Alchemist) | Xe-LPG (Alchemist) | Iris Xe (Gen 12) | Iris Xe (Gen 12) |
| GPU Execution Units | 64 EUs | 192 EUs | 128 EUs (1024 Cores) | 96 EUs (768 Cores) | 96 EUs (768 Cores) |
| Memory Support | TBD | TBD | DDR5-5600 LPDDR5-7400 LPDDR5X - 7400+ | DDR5-5200 LPDDR5-5200 LPDDR5-6400 | DDR5-4800 LPDDR5-5200 LPDDR5X-4267 |
| Memory Capacity (Max) | TBD | TBD | 96 GB | 64 GB | 64 GB |
| Thunderbolt 4 Ports | TBD | TBD | 4 | 4 | 4 |
| WiFi Capability | TBD | TBD | WiFi 6E | WiFi 6E | WiFi 6E |
| TDP | TBD | TBD | 7W-45W | 15-55W | 15-55W |
| Launch | ~2025 | 2H 2024 | 2H 2023 | 1H 2023 | 1H 2022 |









