AMD's Zen 3 core architecture will soon be powering the next-generation Ryzen 4000 desktop and 3rd Gen EPYC lineup. While we have got little hints of what to expect from the upcoming processor architecture, it looks like Adored TV has received some extra information on what Zen3 would have to offer & what PC audiences can expect from AMD's upcoming CPU lineup.

AMD Zen 3 Based Ryzen 4000 And EPYC Milan CPU Rumors - 10-15% IPC Uplift, Increased Cache Per CCX

While we had previously learned that AMD's Zen 3 CPU architecture was going to be a significant uplift in terms of performance and efficiency, Adored TV is saying otherwise. The information he has posted out seems to indicate that Zen 3 would be an evolution over Zen 2 which would make the upcoming architecture a little less impressive than we previously thought so. With that said, let's take a look at the information.

First of all, its mentioned that Zen 3 will include a single CCX consisting of 8 cores. So till now, Zen and Zen 2 had two core complexes on the same die with each CCX consisting of 4 cores. But with Zen 3, each CCX would hold 8 cores so that's essentially a single CCD. Diving further into the core structure of the Zen 3 CCD/CCX, since the CCD has moved to just one CCX, the entire L3 cache can now be shared across all 8 cores rather than each CCX consisting of two slices of L3 caches per CCX in the previous Zen cores. So we have 512 KB of L2 cache per core and 32 MB of L3 cache per CCX or CCD.

Zen 2 also featured 32 MB of L3 cache, but that was split between the two CCX's while Zen 3 will have the full 32 MB of L3 cache available on the same CCD. Another interesting thing pointed out is that 32 MB of L3 cache per CCX would be the absolute limit of what's possible on Zen 3 unlike what was previously suggested in a leaked presentation of Zen 3 which hinted at a possibility of more than 32 MB L3 cache.

Coming to the most interesting bit, it is mentioned that Zen 3 would feature an IPC uplift of 10-15% on a single thread. Interestingly, this is about the same IPC bump in Zen 2 which sounds great but is a little less than what we had initially hoped for or at least what AMD's Senior representatives had hinted in interviews. It is also stated that the 3rd Gen EPYC Milan A0 silicon is currently being tested. Simultaneous Multi-Threading is said to not work on A0 samples but B0 samples which are expected to come out by September would definitely improve upon the older silicon. So if we get to see some early sample benchmarks, then we should take this into account.

In addition to Zen 3, Adored TV also mentions Zen 4 in his post and suggests a couple of new features to be expected on Ryzen 5000 and 4th Gen EPYC Genoa processors such as a new socket, 1 MB of L2 cache per core, support for AVX-512 instructions, further improvement in IPC and fabrication on the 5nm process node.

AMD CPU Roadmap (2017-2022)