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AMD Zen 5 Server CPU Rumors: Turin With Up To 128 Cores, Turin-X With Up To 1.5 GB L3 Cache, Turin Dense With 192 Zen 5C Cores
AMD Zen 5 Server CPU Rumors: Turin With Up To 128 Cores, Turin-X With Up To 1.5 GB L3 Cache, Turin Dense With 192 Zen 5C Cores-February 2024
Feb 12, 2026 11:15 PM

In addition to the Ryzen 8000 leak, information regarding AMD's Zen 5 & Zen 5C powered EPYC Turin, Turin-X & Turin-Dense CPUs have been revealed too.

AMD Readies At Least Five Zen 5 & Zen 5C CPU Families For EPYC Servers: Turin, Turin-X, Turin-Dense, Turin AI & Sorano

Once again, these new rumors come from Moore's Law is Dead latest roadmap which points out the next-generation EPYC CPU families. The roadmap covers at least five EPYC CPU lineups which can be expected in 2024-2025. AMD has already confirmed Turin as its next-gen EPYC family and it will utilize both Zen 5 and Zen 5C cores,

Image Credits: MLID

AMD EPYC Turin & Turn-X With Zen 5: Up To 128 Cores, 4nm Process

Starting with the first family, we have the AMD EPYC Turin (Classic) which will stick with the chiplet design and house up to 128 cores, 256 threads, and TDPs of up to 500W which can be configurable on certain SKUs up to 600W (as revealed in today's Gigabyte leak). In a previous leak, it was shown that the EPYC Turin chips would feature the same L2 and L3 cache as Zen 4 with a small upgrade to the L1 cache.

The major change will come in how AMD arranges the cache on Zen 5 chips which are expected to utilize a "Ladder" hierarchy. The chips are shown to enter production by Q1 2024 & will utilize the TSMC 4nm process node. The actual launch is expected to take place by the third quarter of 2023.

AMD's Zen 5 CPU cores are rumored to feature a brand-new cache design. (Image Credits; AdoredTV)

AMD's Zen 5 CPU cores are rumored to feature a brand-new cache design. (Image Credits; AdoredTV)

Moving on, we have the AMD EPYC Turin-X chips which will be outfitted with a 3D V-Cache. These chips will retain the 64MB of 3D V-Cache per CCD which totals 1024 MB across the 16 CCDs & 512 MB of standard L3 cache. Totaling up to 1536 MB or 1.5 GB of L3 cache. If we combine the L2 cache which is 1 MB per core or 128 MB in total, that increases to 1664 MB of total cache which is still not including the L1 cache. That's a 33% higher cache compared to the upcoming Genoa-X CPU family.

AMD EPYC Turin Dense & Turin AI With Zen 5C: Up To 192 Cores, 3nm Process

Moving over to the Zen 5C side of things, we first have the AMD EPYC Turin Dense chips which will be succeeding Bergamo. Turin Dense isn't an official name for now but it is expected to utilize the 3nm Zen 5C cores in up to 192 core SKUs. These chips will feature up to 500W TDPs but the most interesting thing is that they are expected to hit production before the standard Turin chips. MLID states that this is due to AMD speeding things to compete directly against Intel's Sierra Forest 144 core chips which are also expected around the same time in the first half of 2024.

There's also a secondary Turin Dense chip known as Turin AI which is expected to feature the same Zen 5C cores but with an AI chiplet. There aren't many details regarding this specific SKU but we can expect Xilinx IP to power the AI chiplet for certain applications. AMD is making AI its no.1 strategic priority and it makes sense to incorporate more AI-specific hardware within its EPYC CPUs for the customers that demand it.

Lastly, there's the follow-up to AMD's Siena CPUs known as Sorano. The AMD EPYC 8004 "Siena" lineup makes use of Zen 4/4C cores on the more mainstream and low-cost/low-TCO/low-power platform known as SP6. It has 6-channel memory support and 96 PCIe gen 5 interconnects. These chips will retain up to 64 cores and 225W TDP and production is expected in the 2H of 2024 with availability sometime in 2025.

Image Credits: MLID

AMD has so far announced its upcoming “AMD Data Center and AI Technology Premiere,” which will be the center stage for various server and data center-specific announcements. Definitely expect to hear more about future and upcoming products at the event which is taking place in June.

AMD EPYC CPU Families:

Family NameAMD EPYC VeniceAMD EPYC Turin-DenseAMD EPYC Turin-XAMD EPYC TurinAMD EPYC SienaAMD EPYC BergamoAMD EPYC Genoa-XAMD EPYC GenoaAMD EPYC Milan-XAMD EPYC MilanAMD EPYC RomeAMD EPYC Naples
Family BrandingEPYC 11K?EPYC 10K?EPYC 10K?EPYC 10K?EPYC 8004EPYC 9004EPYC 9004EPYC 9004EPYC 7004EPYC 7003EPYC 7002EPYC 7001
Family Launch2025+2025?2025?202420232023202320222022202120192017
CPU ArchitectureZen 6?Zen 5CZen 5Zen 5Zen 4Zen 4CZen 4 V-CacheZen 4Zen 3Zen 3Zen 2Zen 1
Process NodeTBD3nm TSMC?4nm TSMC4nm TSMC5nm TSMC4nm TSMC5nm TSMC5nm TSMC7nm TSMC7nm TSMC7nm TSMC14nm GloFo
Platform NameTBDSP5SP5SP5SP6SP5SP5SP5SP3SP3SP3SP3
SocketTBDLGA 6096 (SP5)LGA 6096 (SP5)LGA 6096LGA 4844LGA 6096LGA 6096LGA 6096LGA 4094LGA 4094LGA 4094LGA 4094
Max Core Count384?19212812864128969664646432
Max Thread Count768?38425625612825619219212812812864
Max L3 CacheTBD384 MB1536 MB384 MB256 MB256 MB1152 MB384 MB768 MB256 MB256 MB64 MB
Chiplet DesignTBD12 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD16 CCD's (1CCX per CCD) + 1 IOD8 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (2 CCX's per CCD) + 1 IOD4 CCD's (2 CCX's per CCD)
Memory SupportTBDDDR5-6000?DDR5-6000?DDR5-6000?DDR5-5200DDR5-5600DDR5-4800DDR5-4800DDR4-3200DDR4-3200DDR4-3200DDR4-2666
Memory ChannelsTBD12 Channel (SP5)12 Channel (SP5)12 Channel6-Channel12 Channel12 Channel12 Channel8 Channel8 Channel8 Channel8 Channel
PCIe Gen SupportTBDTBDTBDTBD96 Gen 5128 Gen 5128 Gen 5128 Gen 5128 Gen 4128 Gen 4128 Gen 464 Gen 3
TDP (Max)TBD480W (cTDP 600W)480W (cTDP 600W)480W (cTDP 600W)70-225W320W (cTDP 400W)400W400W280W280W280W200W

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