The Intel Sapphire Rapids-SP Xeon CPU family specifications have also been leaked which feature a total of 46 SKUs planned for the Eagle Stream platform.

Intel Readies At Least 46 Sapphire Rapids-SP Xeon CPUs As Specs Leak Out: Flagship Platinum 8490H With 60 Golden Cove Cores, 350W Base TDP

For Sapphire Rapids-SP, Intel is using a quad multi-tile chiplet design which will come in HBM and non-HBM flavors. While each tile is its own unit, the chip itself acts as one singular SOC and each thread has full access to all resources on all tiles, consistently providing low-latency & high cross-section bandwidth across the entire SOC.

We have already taken an in-depth look at the P-Core over here but some of the key changes that will be offered to the data center platform will include AMX, AiA, FP16, and CLDEMOTE capabilities. The Accelerator Engines will increase the effectiveness of each core by offloading common-mode tasks to these dedicated accelerator engines which will increase performance & decrease the time taken to achieve the necessary task.

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In terms of I/O advancements, Sapphire Rapids-SP Xeon CPUs will introduce CXL 1.1 for accelerator and memory expansion in the data center segment. There's also an improved multi-socket scaling via Intel UPI, delivering up to 4 x24 UPI links at 16 GT/s and a new 8S-4UPI performance-optimized topology. The new tile architecture design also boosts the cache beyond 100 MB along with Optane Persistent Memory 300 series support. The lineup will also come in HBM flavors which will be using a different packaging design:

Intel Sapphire Rapids-SP Xeon (Standard Package) -4446mm2Intel Sapphire Rapids-SP Xeon (HBM2E Package) -5700mm2AMD EPYC Genoa (12 CCD Package) -5428mm2

Intel Sapphire Rapids-SP Xeon CPU Platform

The Sapphire Rapids lineup will make use of 8-channel DDR5 memory with speeds of up to 4800 Mbps & support PCIe Gen 5.0 on the Eagle Stream platform (C740 chipset).

The Eagle Stream platform will also introduce the LGA 4677 socket which will be replacing the LGA 4189 socket for Intel's upcoming Cedar Island & Whitley platform which would house Cooper Lake-SP and Ice Lake-SP processors, respectively. The Intel Sapphire Rapids-SP Xeon CPUs will also come with CXL 1.1 interconnect that will mark a huge milestone for the blue team in the server segment.

The final 4th Gen Sapphire Rapids-SP Xeon CPU with its multi-chiplet design housing Compute & HBM2e tiles. (Image Credits: CNET)

Coming to the configurations, the top part is started to feature 60 cores with a TDP of 350W. What is interesting about this configuration is that it is listed as a low-bin split variant which means that it will be using a tile or MCM design. The Sapphire Rapids-SP Xeon CPU will be composed of a 4-tile layout with each tile featuring 14 cores.

Now based on the specifications provided by YuuKi_AnS, the Intel Sapphire Rapids-SP Xeon CPUs will come in four tiers:

Bronze Tier: 150W TDPSilver Tier: 145-165W TDPGold Tier: 150-270W TDPPlatinum Tier: 250-350W+ TDP

The TDPs listed here are at PL1 rating so the PL2 rating, as seen earlier, is going to be very high in the 400W+ range and the BIOS limit is expected to hover at around 700W+. Compared to the last listing where most of the SKUs were still in the ES1/ES2 state, the new specs are based on final chips which will be hitting retail.

Intel will offer various SKUs with the same but different bins, affecting their clocks/TDPs. For example, there are four 44 core parts with 82.5 MB cache listed but clock speeds should vary across each SKU. There's also one Sapphire Rapids-SP HBM 'Gold' CPU in its A0 revision which has 48 cores, 96 threads, and 90 MB of cache with a TDP of 350W. The flagship of the lineup is the Intel Xeon Platinum 8490H which offers 60 Golden Cove cores, 120 threads, 112.5 MB of L3 cache, 2.9 GHz all-core boost clocks, and a base TDP figure of 350W. Following is the entire SKU list that has been leaked:

Intel's Sapphire Rapids-SP Xeon CPU family specs have been leaked. (Image Credits: Yuuki_AnS)

Intel Sapphire Rapids-SP Xeon CPU SKUs List (Preliminary):