Intel appears to be readying to take a step towards the Multi-Chip-Module (MCM) approach, following in the steps of AMD with its Ryzen Threadripper and EPYC Rome and Naples HEDT and server processors with their chiplet designs, with the initial patent detailing silicon bridge technology.

Intel Silicon Bridges - MCM Alternative to Interposers

As the size of silicon dies continue to become larger and push the boundaries of process technology and manufacturing, alternative methods of increasing performance must be taken into account. For AMD, Multi-Chip-Module technology had been the method of choice to continue to push increased performance without the need for a process shrink.

AMD FX Piledriver 'Vishera' CPUs have a die size of 315mm2, and 'Abu Dhabi' Opteron CPUs have exactly double this due to the implementation of two Bulldozer dies at 630mm2, linked together through the use of HyperTransport 3.0. This is similar to AMD's current Threadripper and EPYC CPUs, as the technology found in these processors, Infinity Fabric, is a superset of the HyperTransport protocol.

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In the case of AMD's MCM design implementation within Opteron, core scalability is highly efficient, allowing for nearly linear performance gains, doubling the total die area, and in doing so, also doubling core count. Threadripper and EPYC are no different. AMD's Zeppelin die for Zen CPUs measured to have an area of 213mm2 packing eight cores, and with Infinity Fabric, implemented within Threadripper, for example, AMD is enabled to wire up two dies together for a total of 226mm2 and sixteen cores, scaling nearly perfectly.

Interposer Technology - Yields, Costs, & Transfer Boundaries

With current interposer implementations, such as chips that contain High Bandwidth Memory (HBM), the primary chip, such as a GPU, is attached to the top of the interposer, similarly to the HBM module, with the interposer being soldered to the package substrate. Due to this stacked design, Through-Silicon Vias, or TSVs, are required to pass data from the GPU down to the interposer, and then relay that data across the interposer back up to the HBM. The use of TSVs introduces an issue with potential yields. If one TSV is at-fault within the interposer, the entire interposer is defective.

Interposer Versus Silicon Bridge Diagram

Package Substrate as Interposer Replacement